Samsung Electronics confirmed this week that it has begun mass production of HBM4, becoming the first company to manufacture sixth-generation high-bandwidth memory at commercial scale. The milestone demonstrates a fully vertically integrated production flow combining DRAM fabrication, logic die manufacturing on a 4-nanometer node, advanced packaging through thermal compression bonding, and final testing, all within Samsung’s own facilities. No other semiconductor company possesses the combination of memory, logic, and packaging capabilities required to produce HBM4 entirely in-house.
The production flow begins at Samsung’s Pyeongtaek campus, where DRAM wafers are fabricated using the proprietary 1b-nanometer DRAM process. Each wafer produces hundreds of memory dies that are thinned to approximately 30 micrometers. The thinned dies undergo probe testing before being sorted for stacking. Simultaneously, the logic die is fabricated at Samsung’s Giheung or Hwaseong foundry on the 4-nanometer Gate-All-Around process, a chip that manages data flow, error correction, power delivery, and thermal monitoring for the entire memory stack.
The packaging stage is where vertical integration delivers its most tangible advantage. The 12 tested DRAM dies and the logic die are assembled into a single stack using thermal compression bonding, with each bonding step achieving alignment accuracy within one micrometer and temperature uniformity within two degrees Celsius. The process is repeated 12 times to build the full stack, with each additional layer introducing cumulative risk: a bonding failure at any layer renders the entire stack defective, making yield management the central manufacturing challenge.
SK Hynix produces HBM through a disaggregated supply chain. Its DRAM dies are fabricated internally, but the logic die is manufactured by TSMC, and the packaging process depends on both internal capacity and outsourced assembly partners. This disaggregation introduces coordination complexity and supply allocation risk that Samsung’s integrated model avoids. The tradeoff is that TSMC’s logic die process technology offers superior power efficiency, meaning SK Hynix’s HBM4 may consume less power per operation.
For investors evaluating Samsung’s competitive position in HBM, the manufacturing process is the foundation on which financial performance rests. Vertical integration reduces production costs by eliminating external margin, shortens cycle time by consolidating production scheduling, and provides engineering feedback loops that accelerate yield improvement. These advantages are structural, persisting regardless of short-term competitive dynamics. The question for 2026 is whether Samsung can scale this integrated process to volumes that meaningfully increase its HBM market share from the approximately 35% it held in Q3 2025.
